The Great Repackaging

Open a server from 2012 and you are looking at a map of the semiconductor industry. Every socket on the motherboard is a market. The CPU socket belongs to Intel. The rows of memory slots belong to an oligopoly consolidating toward three companies (MU, SK Hynx, and SanDisk). The graphics card in the PCIe slot belongs to Nvidia, back when Nvidia sold ingredients. The network card, the voltage regulators crowded around the processor. Each a separable purchase, a separate price, a separate stock you could own. The board is the industry, drawn to scale.

Now open a compute tray from Nvidia's rack generation that began shipping in volume this year; Vera Rubin, 2026. The memory is not in slots; it is stacked inside a sealed package on the processor's shoulders, closer to the GPU than the GPU is to its own power connector. The optical links that connect this tray's rack to its neighbors still arrive as pluggable modules snapped into switch faceplates (an entire merchant industry) and they are scheduled to follow the memory inward. Socket by socket, the map is being redrawn.

Notice precisely what disappears when a socket does. Not the function... the memory still exists, and there is more of it than ever. Usually not the supplier either. What disappears is a bundle of rights: who specifies the component, who chooses its supplier, who qualifies it, who negotiates its price, who can replace it without redesigning the system. On the old board, those rights sat with the buyer, governed by open standards. This installment's claim, stated up front so the evidence can be read through it: the useful unit of analysis in AI hardware is no longer the component but the boundary (that bundle of rights) and every physical crossing puts the bundle back on the table. Physical integration is the mechanism; the renegotiation of rights is the event, and value capture follows the rights, not the silicon. Part 1 tracked scarcity rotating across the stack. Underneath that rotation runs a slower, so-far-persistent inward current. Components are what the market prices at the end of the day. But boundaries are where the repricing happens realistically.

The physical ladder story scales: a die sits inside a package, which mounts on a board, which slides into a tray, which stacks in a rack, which lives in a building. The deepest moves happen at the package, but the same pressure around performance-critical functions is pulled toward tighter proximity and tighter architectural control. This redesigns the board, tray, and rack around the package.

Scaling changed address

For fifty years, the industry had one address for progress: the transistor. Make it smaller, get more of them, everything downstream improves. That engine hasn't died, but it has slowed and grown expensive. The new process nodes arrive later, cost more, and deliver less per step.

The response was not to accept the slowdown but to move the scaling: from the transistor to the package. If you can no longer double what's on one die, put several dies in one package (chiplets). If the dies need to talk at extreme speed, mount them on a silicon interposer millimeters apart (2.5D). If millimeters are too far, stack them vertically (3D). Each step keeps performance compounding by shrinking a different variable. Which is not the transistor, but the distance between transistors that need each other.

Why distance? Because at these speeds, moving data can cost more than computing with it. Pushing a bit across a board can burn more energy than the arithmetic performed on it at arrival; pushing it a few millimeters across an interposer costs a small fraction of that. AI made this brutal, because AI workloads are exercises in moving staggering volumes of data between memory and processor. The constraint engineers call the "memory wall". Packaging is the industry's principal answer to it (software has another; we'll get there). Proximity became the product.

Note the paradox inside this, because it is half the thesis. A chiplet-era package is not a monolith; it is a collection dies, memory stacks, interposer, substrate, often from different suppliers. Integration does not eliminate modularity. It relocates it to boundaries that used to sit on the motherboard. Which was priced by the market and governed by industry standards. Now it is governed instead by a private web of co-design contracts among platform designer, foundry, memory supplier, and customer. "Internal" rarely means internal to one corporation; it means administered rather than open.

Openness is a spectrum though. An interface can be technically standardized yet qualification-constrained; multi-sourced yet governed by one reference architecture; open in specification yet expensive to leave. The question that decides who profits is not whether interfaces exist (they always will) but how many of the boundary's rights stay negotiable after it moves. Keep that question in hand; the essay turns on it.

Four boundaries, at four stages of proof

The crossings run in a rough order. Set mostly by how badly each function suffers from distance, bent by yield, serviceability, and customers' appetite for vendor integration. Read them as a maturity spectrum: the first is commercial history, the second an active transition, the third a roadmap, the fourth a projection.

Memory: settled evidence. In 2015, a graphics card shipped with its memory stacked on an interposer beside the GPU. Which was the first high-bandwidth memory in production.¹ A decade of commercial history later, HBM runs 30 to 40 percent of an AI accelerator's manufacturing cost by analyst estimates, and the memory inside Nvidia's rack captured more of the last generation's cost increase than the GPU did.² The memory slot survives via host DRAM lives on, and grows. But the performance tier left the board, and no current roadmap brings it back.

Networking: transition in progress. The pluggable optical transceiver is moving onto the switch silicon (the switch's package, note, not the accelerator's). Co-packaged optics cuts the power of a 1.6-terabit link from roughly 30 watts to 9 by removing the electrical distance the signal used to travel.³ First hyperscaler deployments began in 2026; analysts put scale at 2028–2030, with pluggables persisting as the majority of links well past that.⁴

Power delivery: roadmap. You cannot feed kiloamp currents across a board to a 2-kilowatt processor without losing to resistance; the final stage of voltage conversion is headed onto or under the die, with the surrounding rack re-architecting to 800-volt DC to cope. A rack-level redesign forced by a package-level fact.⁵ Vendors say around 2028. Roadmaps slip.

Cooling: projection. When the heat source is a stack of dies, the cold plate wants to merge with the thing it cools; microfluidic channels etched into the silicon appear on vendor roadmaps near 2030.⁶ The most speculative rung, and weighted accordingly.

Note what even the settled crossing did not delete the old market. Host DRAM, pluggable optics, rack power supplies, facility cooling loops. The residual tiers persist, sometimes for decades. Integration takes the highest-performance, fastest-growing tier; the board keeps the rest; often large, sometimes profitable, no longer where the design authority lives.

Every absorption is three events

Here is the framework this series will keep reusing. When a function crosses a boundary, one announcement contains three distinct events with three distinct investment meanings.

A socket dies. Read "socket" economically, not mechanically: what dies is an independently negotiated interface. A purchase that used to be priced, sourced, and swapped on the open market. The vendor selling into it faces displacement, the event the market prices first and most fully; the pluggable-transceiver makers already trade on it.

Scope shifts usually toward an integrator, rarely entirely. Design authority, qualification control, and procurement that used to be negotiated at the socket move inside someone's product boundary. But "someone" is often several parties. Platform designer, foundry, component supplier, and customer can end up contesting the same relocated rights. Scope is a leading indicator of power, not proof of it; whether it hardens into margin travels through specific channels. Co-design entanglement, qualification friction, contract length, switching cost and those channels, not the physical integration itself, are what an investor should verify.

A seam opens sometimes. By seam I mean the new interface an absorption creates and the external supplier niche that forms around it. Co-packaged optics created sudden strategic demand for precision fiber-alignment components made by a handful of Japanese suppliers —(Sumitomo Electric, Senko, Fujikura). That most investors had filed under legacy telecom parts.⁷ The interposer era did the same for advanced packaging, now described by TSMC as rivaling wafer fabrication in difficulty.⁸ An adjacent case makes the mispricing mechanism vivid: when advanced packages needed a specialized insulating film, the critical supplier turned out to be Ajinomoto. A seasonings company whose build-up film became a chokepoint the market had filed under food.⁹ That one is a materials chokepoint rather than a new interface, but it teaches the same lesson: the market is often late because the relevant suppliers are screened under the wrong category. Classification lag is one mechanism of that lateness. Small initial categories, private qualification, and diluted supplier economics are others.

The counter-case sets the framework's limit. When CPUs absorbed the memory controller in the late 2000s, the northbridge (an entire merchant chipset market) died on schedule, the CPU vendors took the scope, and no investable seam opened. The new interface stayed internal to the integrators, and the chipset vendors simply exited.¹⁰ The refinement that survives: seams pay only where the new interface demands capabilities the integrator cannot economically internalize. Exotic materials, precision assembly, specialized test. Where the integrator can swallow the complexity whole, the seam is real but private, and there is nothing to buy.

One warning before applying any of this: the two triads of this series do not map one-to-one. Socket-scope-seam describes what a crossing does; Part 1's three questions grade what it's worth. A dead socket is not automatically pricing power, scope is not automatically structural dollars, and a seam is not automatically a moat.

Case study: memory crosses twice

Now run the framework on one boundary (memory) which supplies two crossings, a decade apart, that pay two different debts from Part 1.

The first crossing pays question two where the structural dollars flow. Memory entered the package in 2015 for a physical reason: distance made bandwidth the expensive ingredient, and stacking memory beside the processor was the only way to feed it. The crossing created the possibility; the workload keeps choosing it. Model demand for moved bytes keeps outrunning compute, so each generation adds stacks, capacity, and wider interfaces. Which is why HBM bandwidth per flagship rack roughly tripled between the GB300 (2025) and Vera Rubin (2026) generations, with stack counts, capacity, and packaging content moving the same direction.² Bandwidth alone is not dollars. The dollar claim also runs through stack count, die area, and packaging cost. But in this cycle all of those rose together, independent of the price spike layered on top. That is the content mechanism: physics explaining rising quantity. It says nothing yet about who profits.

The second crossing pays question three whether anyone captures durable margin and it is happening now. By HBM4, the memory is already inside the package; what crosses this time is not the product but control. Starting with the HBM4 generation shipping in 2026, the controller die at the base of the memory stack moves to advanced foundry manufacturing, and in some designs carries circuitry specified by the end customer.¹¹ Customization, logic, and qualification authority migrate deeper into the stack. A second-order crossing, and evidence for something the first couldn't show: boundaries keep moving after a function integrates. Entry into the package is where the renegotiation moves indoors.

Run the three events, and let them land unevenly, because they do. The socket event is strong: interchangeability. The defining property of commodity memory declines sharply, as products become qualified, customer-specific variants rather than fungible parts. Qualification stops being a formality and becomes the market; one analyst assessment holds that Micron is effectively absent from the first Rubin-generation supply wave. A disputed, single-source claim, offered here as illustration rather than load-bearing evidence. And if right, that is exclusion from a generation, not a lost quarter.¹²

The scope event is strong too, but it is a contest, not a coronation: Nvidia holds the reference architecture, the foundry collects a toll inside the DRAM stack, the memory vendor gains lock-in, and the biggest buyers probe from the other side. The same rack teardown that prices Vera Rubin at $7.8 million estimates $6.7 million if the hyperscaler procures memory directly.¹³ Four corners pulling at one relocated boundary.

The seam event is the least proven of the three. Custom base-die design capacity and per-customer qualification pipelines are commercially decisive. But so far they live mostly inside the incumbents memory vendor, foundry, platform designer. Whether a publicly investable third-party niche forms here is not yet clear, and the framework permits that answer: the northbridge taught us some crossings produce no public seam. This one may be a socket-and-scope story.

For the supplier, being designed into the package is a promotion and a cage: the customer finds you harder to replace, and you find the customer harder to leave. Higher stakes per decision, fewer decisions.

Two counterarguments: demand and ownership

The thesis faces two serious attacks that target different things: one challenges the demand for the functions moving inward, the other challenges whether anyone gets to own the boundaries they cross.

Software attacks demand specifically, the memory-content leg. The case above assumes AI systems keep demanding more bytes moved per unit of intelligence. Engineers attack that daily: four-bit number formats that halve a model's working-state footprint,¹⁴ architectures that activate a fraction of their parameters per token, attention variants that shrink the cache the package exists to feed. If bytes-per-token falls faster than tokens grow, the content mechanism erodes; optics, power, and cooling have their own distance problems and would feel it only indirectly. So far the pattern is the one Jevons documented when efficient steam engines increased Britain's coal consumption: efficiency gets spent. Nvidia advertised its latest format's halved memory cost as doubled context and concurrency.¹⁵ But "so far" is carrying weight, and a model family that meaningfully reduced reliance on stored state would weaken the memory wall itself. Hard to price, easy to describe: falsifier material.

Standards and buyer power attack ownership the deeper threat. Physical integration converts into economic control only if the relocated rights stay administered. The largest buyers are working to prevent that: open chiplet interconnect standards aim to make package internals substitutable across vendors¹⁶. Hyperscalers are testing disaggregated procurement of package contents (the direct-memory probe above); open fabric coalitions exist precisely to stop any single integrator from administering the interfaces between packages. The strongest version of the attack says the boundary can migrate inward while the negotiation stays open. Control ends up distributed and contested rather than concentrated. Note what that outcome would and wouldn't break: it would weaken the integrator-power story, but the boundary would remain the right unit of analysis the rights still moved. They just landed in more hands. Part 1 asked whether customers can route around a supplier after scarcity clears. This is the same question one level down: can customers re-open a boundary after it closes? History says sometimes yes which is why scope is a leading indicator and never proof.

What would prove this wrong

Falsifiers matched to the leg they test.

Optics (the transition). If co-packaged optics is below roughly ten percent of new 1.6-terabit-class switch ports by end-2028, the networking crossing stalled, and the seam suppliers were a windfall, not a wave.⁴

Memory de-commoditization (the second crossing). Buyer count is the wrong gauge; two hyperscalers could be most of the volume. The right one: if customer-specific base dies stay below a meaningful share of HBM4E volume (call it a fifth) by 2028, or fail to persist into the following generation, question three's mechanism loses its teeth.

Memory content (the first crossing). Physical content, not bandwidth alone and not dollars: if capacity, stack count, and bandwidth per flagship rack go flat together at the Rubin-Ultra-to-next transition (2027 to roughly 2029), the content leg fails. That leg, not the whole thesis.

The economic mechanism itself (the master claim). If functions keep moving physically inward while the commercial signatures stay flat. Wualification periods not lengthening, component contracts not extending, hyperscaler direct procurement of package internals rising rather than falling, supplier concentration at the new interfaces unchanged — then the boundaries moved and control didn't, and this framework describes engineering rather than economics.

This last one is empirically messier than the technology falsifiers, and the gauges must be cycle-adjusted: a long-term agreement signed during a shortage proves scarcity, not structure. The real test is persistence after scarcity eases. Whether custom variants, long qualification, and administered procurement survive into the next downcycle. The repeatable public proxies exist in filings. Long-term-agreement coverage, customer prepayments, qualification announcements imperfect gauges, printed quarterly.

The reframe to carry forward: for decades, the investable question in hardware was which component wins. The repackaging makes it which boundary is being redrawn, and how many of its rights stay negotiable afterward. Durable margin is never automatic; it is Part 1's third question, relocated inward, and it must be earned crossing by crossing.

Which brings the series to its least "mysterious cliffhanger". The participant that sets the reference designs and ships on an annual clock is, of course, Nvidia. The genuine questions are the ones this essay has armed you to ask (hopefully): how architectural authority over the boundaries is actually maintained, what keeping it on an annual clock costs, and whether foundries, standards bodies, and Nvidia's own largest customers. The ones probing every boundary from the other side can unbundle it. That is Part 3.

Sources and confidence notes

AMD "Fiji" GPU (Radeon R9 Fury X) with first-generation HBM, June 2015. Historical record.

HBM share of accelerator manufacturing cost: analyst estimates, 2025–26. Rack cost-capture, bandwidth, stack-count and capacity comparisons: Morgan Stanley Vera Rubin bill-of-materials analysis, May 2026, and Nvidia platform specifications — analyst estimate and vendor specification respectively (see also Part 1, notes 6–7).

Nvidia co-packaged optics engineering publications (Spectrum-X Photonics materials), 2025–26. Vendor figures.

Yole Group optical-interconnect projections and OFC 2026 conference reporting. Analyst projection; also the basis of the optics falsifier and its threshold.

Nvidia 800-VDC architecture white paper and GTC 2026 materials. Vendor engineering rationale; timing is roadmap.

Vendor and research-consortium roadmaps for in-silicon microfluidic cooling (Nvidia, imec and others), 2025–26. Projection.

Trade reporting on precision fiber-alignment suppliers (Sumitomo Electric, Senko Advance, Fujikura), 2026. Industry reporting; specific outlet citations to be attached before publication.

TSMC public commentary and industry analysis on advanced-packaging difficulty and capital intensity, 2025–26. Qualitative consensus.

Ajinomoto Build-up Film (ABF) substrate shortages, 2020–22. Historical record; used as an adjacent illustration of classification lag, not as a seam in the framework's strict sense.

Integration of the memory controller into CPUs (AMD from 2003; Intel Nehalem, 2008) and the subsequent exit of merchant northbridge/chipset vendors. Historical record.

HBM4 base die on foundry logic processes with customer-specific variants: SemiAnalysis reporting and memory-vendor announcements, 2025–26. Analyst reporting on announced architecture.

SemiAnalysis assessment, February 2026. Single-analyst claim, disputed by the vendor's contract narrative; illustrative, not load-bearing.

Morgan Stanley, May 2026. Analyst estimate.

Nvidia NVFP4 format documentation: ~50% working-state memory reduction versus FP8. Vendor figure.

Nvidia technical blog framing of NVFP4 benefits as doubled context/concurrency. Vendor framing; the rebound interpretation is the author's.

UCIe (Universal Chiplet Interconnect Express) consortium specifications and membership, 2022–26. Industry standard; adoption breadth in AI accelerators remains limited to date, which is why this is presented as a counterforce rather than a fact on the ground.